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[Eng. /Esp.]
This all started with a question: “What kind of original, exclusive pictures could shoot an insane computer architect who loves photography?” This first try is a double exposure showing (second shot) the screen of a host computer with the signals of a MIPS pipelined processor implemented in VHDL on a FPGA, running a simple loop, superimposed to (1st shot) the actual FPGA development board to which the VHDL cross-compiled code has been transferred. RAW image imported in LR5.5, just applying the default Vivid Nikon Picture Control setup. Warmly devoted to my colleage Dr. J. Resano and our students.
~~~~~
Todo esto comenzó preguntándome: “¿Qué tipo de fotografías originales y exlusivas podría hacer un arquitecto de computadores loco de atar al que le gusta la fotografía?”. Este primer intento es una doble exposición que muestra (primer disparo) la pantalla de un computador principal con las señales de un procesador MIPS segmentado implementado en VHDL sobre una FPGA, que está ejecutando un bucle simple, sobreimpuesta a (primer disparo) la placa de desarrollo real con la FPGA a la que se ha transferido el código VHDL tras compilación cruzada. La imagen RAW está importada en LR5.5, aplicando simplemente el perfil Vivid de Nikon. Dedicada con afecto a mi colega el Dr. J. Resano y a nuestros estudiantes.
En inglés porque quien sepa qué es un FPGA, sabe inglés y no necesariamente español.
If it was accidental, is it still "art"?
This is my cellular automata FPGA project in an early stage of development. I was having some RAM reading/writing problems. I learned the hard way that "10ns RAM" doesn't mean you can access it reliably at 100MHz. Violating memory timings and outputting the result to a CRT display results in very interesting imagery.
I developed this project for my computer architecture course in November, 2006. It was implemented on a Spartan3 Starter Kit development board. The system's inputs were all the switches and buttons on the board, plus a PS/2 mouse. The output was a VGA display. This image was obtained by photographing said display.
The output of the completed project can be seen in the images that follow this one in my photostream.
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
This is a quick and dirty demo of my video synthesizer. It is basically an FPGA board connected to an old CRT display. It is meant for live performance. The images were recorded using a webcam. No fancy effects or editing, just cut and paste.
The synthesizer's inputs are:
-4 switches
-4 push buttons
-1 knob
-1 keyboard
These are used to control the color, size, rotation and complexity of the polygons.
Output:
-640x480 @ 60Hz, 8-color VGA
Yes, eight fabulous colors.
How does it work?
It basically renders a wire frame model. The vertices of the model can be moved around using the keyboard. You don't really have much control over the shape. The keyboard is sort of a "random data source", which means the user just bashes the keyboard like a monkey until something pretty shows up on the screen ;). More precise controls could be easily implemented, but I am happy with them as they are now.
Having a cheap webcam to "post-process" the video is very important. It is the key overcome the 8-color limitation imposed by the FPGA board. The digital-to-analog-to-digital conversion process helps to soften the colors, and makes the resultant images look better. The colored dots you see are actually the phosphor sub-pixels of the CRT display. The camera I used was a Microsoft LifeCam VX-3000.
The actual digital circuit that's the core of the synthesizer started out as a school project. It took me about 3 weeks to develop. Then I modified it so I could have more control over the image, and to make sure there were glitches everywhere :).
If you want any more info (VHDL code even!), please contact me. My email is: checo22 {at} google's email service.
MUSIC BY ORVONTON (available as a free download)
myspace.com/orvonton
I perform with these guys:
emulacionaleatoria.com
More info on the FPGA board here:
xilinx.com/s3estarter
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
Check out the video: www.youtube.com/watch?v=R1_U43JD8g4
Get the code here: github.com/armandas/FPGalaxy/tree/v1.0
Animated gif: github.com/armandas/FPGalaxy/blob/master/graphics/scene.gif
High definition image sensors 1M pixel combined with reprogrammable Virtex6 FPGA that includes a 32bit softcore processor programmed under CPP. All video paths streamed in near realtime. The printed circuit board is designed for high reliability and ease of manufacture. Image sensors and main board curvature are folded into position at a final assembly stage using an inner flex interconnect PCB combined with inner and outer FR4 component layers.
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
Vectrex Console circa 1982
8-bit game machine residing outside a cube at work...
CPU : Motorola 68A09 @ 1.6 MHz
RAM : 1 KiB (two 4-bit 2114 chips)
ROM : 8 KiB (one 8-bit 2363 chip)
Display : Samsung Model 240RB40
Sound : Single Speaker Mono
lomo "look" by ACR+PS, original seen here
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
This is the output of a Cellular automata system developed using a Spartan 3 Starter Kit FPGA board. The user could pause the automata, change the frame rate, apply 16 different rules (Conway's life, Brian's brain, parity, lichens, time tunnel, Greenberg, among others), seed it with a mouse-drawn pattern and choose among two color palettes.
Some features and numbers for the curious:
-Resolution: 320x240
-Inputs: 8 switches, 4 push buttons, PS/2 mouse
-Output: 3-bit VGA
-Colors: 27 (using temporal and spatial dithering)
-System clock: 30MHz max.
-Moore neighborhood.
-16 rules (limited only by the number of switches, more rules can be trivially added).
These pictures were obtained by photographing the CRT display that received the VGA signal.
More info here, and the rest of the pictures are on my photostream. If you are interested in the VHDL source code, please let me know. I will gladly share it with anyone.
Disclaimer: These pictures were edited using Photoshop to increase contrast and in some cases color inversion has been applied. Color inversion was not a feature of this system, but it can be trivially implemented.
HS02 Headset was redesigned from three 50MHz DDS drivers to a single channel driving one Tx coil. The head worn assembly, mounted into a cap, includes multiple sensor feeds ranging from RADAR ;-) to Gyroscope, compass, HD Image sensors, Accelerometers, Ultrasonics, LASER, RF transceiver, IrDA, DDS coil driver, IR eyelid detect, ADCs, all running over a Virtex6 FPGA.
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
Today I've managed to finish up the hard part, building the VHDL code to interface to the SDRAM chip & act as a dumb framebuffer - It's a little slow at the moment but works very well.
Wasn't so sure it was going to go smoothly as I had some fun corruption issues earlier, but that turned out to be that I had accidentally reversed some address pins in the FPGA pinout.
This design is currently occupying 16% of the slices on the Spartan-6 FPGA - plenty of room for future experimentation!
New state machine being added to FPGA core Feb2014
Sam donating his time and extensive VHDL expertise to continue vital work on a state of the art neural stimulator test frame. Generating drivers for various hardware components including; ADC, DAC, Crosspoint switch, VNA, UART, SD Card, 2.4GHz transceiver, Display.
The Nexys 4 DDR is a drop-in replacement for our cellular RAM-based Nexys boards. Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, a temperature sensor, MEMs digital microphone, speaker amplifier and plenty of I/O devices allow the Nexys 4 DDR to be used for a wide range of designs without needing any other components. The most notable improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
Dual High Definition HD image sensors operating via a Virtex6 FPGA Hardware includes DRAM, SRAM, Audio Codecs, HDMI Controller. DDS Coil Drivers, Gyroscopes, Compass, Accelerometers, MICS RF Transceiver, Ultrasonics, LASER, Encrypted EEPROM, unique ID, SFLASH, IrDA, Microphone Array.
I recently purchsed a Basys2 FPGA development kit to learn about designing hardware using these interesting devices and developing some new projects that are more advanced and greater performing than ever would of been possible before.
Xilinx Spartan3E board from Digilent. This is the work horse of my electronics toolkit.
You can get your own here.
They also have some material on learning vhdl.
No tuve mucho tiempo de jugar con los colorcitos de los autómatas. La mayoría de estas fotos las tomé en un intervalo de dos horas la noche anterior a la entrega del proyecto.
Cada una es el resultado de varios cientos de iteraciones, con reglas y semillas cambiantes. Son, en la práctica, irrepetibles. En funcionamiento normal, cada imagen duraba en pantalla unos dieciséis milisegundos, y en seguida era reemplazada por otra. El hecho de ser tan efímeras les da un valor especial, creo yo. Se les podía contemplar un brevísimo instante, y nunca más se veía otra igual. En verdad, así son todas las cosas.
No soy yo el autor. Tiré una piedra en el centro de un lago y me maravillé con las ondas y peces coloridos que vi brotar de él. Tremenda agitación por la más pequeña de mis intervenciones. Un pequeño universo con sus propias dimensiones y leyes. No me cansé de verlo ora evolucionar, ora estancarse; quedarse a veces totalmente inerte, y otras devenir en un gran caos. Verdaderamente admirable es que todo ello esté contenido, a su vez, en un universo del cual yo soy parte.
Espero haber despertado curiosidad en algún lector.
...regular guy by night. Here's me hard at work (well, maybe not if I'm taking pictures). The work is really great though. You can see that rack in the background, that's where we put the development boards. We'll then hook up power and some ethernet cords and then make some tests with Tcl ("tickle" the programming language) to run regularly to make sure the software is working.
I really like it a lot. I've got my own whole desk with my own bookshelf (they supplied us with all sorts of technical books like Linux Kernel Development, and VHDL for Designers, and Tcl/Tk In A Nutshell).
Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors.
store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-bo...
PmodGPS: GPS Receiver
The PmodGPS can provide satellite positioning accuracy to any embedded system. By communicating through UART with the GlobalTopFGPMMOPA6H GPS antenna, users may benefit from the 3 meter accuracy for any long term traveling.
store.digilentinc.com/pmodgps-gps-receiver/
PmodGYRO: 3-axis Digital Gyroscope
The PmodGYRO is a 3-axis gyroscope powered by the STMicroelectronics L3G4200D. By communicating with the chip through SPI or I2C, users may configure the module to report angular momentum at a resolution of up to 2000 dps.
store.digilentinc.com/pmodgyro-3-axis-digital-gyroscope/
PmodHB5: H-bridge Driver with Feedback Inputs
The PmodHB5 is a 2A H-Bridge module. This module includes a header with integrated motor feedback channels with Schmitt-trigger inputs. The H-Bridge can be driven through GPIO signals.
store.digilentinc.com/pmodhb5-h-bridge-with-feedback-inputs/
PmodISNS20: 20A Current Sensor
The Digilent PmodISNS20 is a small current sense module with a digital SPI interface. The board combines an Allegro ACS722 Hall Effect current sensorwith a 12-bit analog-to-digital converter from Texas Instruments. The PmodISNS20 is quick, accurate, and easy to use for a variety of applications.
Matrix shows Compass bearing mapped to Horizontal Axis while Vertical Axis shows elevation mapped to +/-90deg..
Distance to target displayed as intensity. The video RGB target average also mapped to assist in image to acoustic object translation.
This is a scene from my implementation of Pong game in VHDL on Xilinx Spartan-3E board.
You can watch a video here: www.youtube.com/watch?v=IBhdHHIXBtY
Get the code: github.com/armandas/Plong/tree/v1.0
Live left Image sensor headset view of VRL Laboratory. Mirror to the right of the screen shows a rear facing view of the left eye.
This rear facing mirrored section of the screen remains static relative to head centric movement and subsequently provides a secondary video path to capture the eye (pupil) gaze allowing a means of controlling projected image to a high acuity excitation chip.
Perceptual reconstruction of a scene via tracking of the left and right eye gaze allows a means of targeting RGB and distance to objects that subsequently provide an alternative means of user controlled (eye-scanning) binaural acoustics.
Real Time Video Motion Detection Derived from High Definition Image Sensor and Automatically Scaled to a 16x16 Grey Scale Matrix. 16x16 matrix designed to provide real time signal path to bionic eye 16x16 CMOS MEA.
This book uses over 75 examples to show you how to get started designing digital circuits in VHDL or Verilog®, simulate them, and quickly and easily download them to your Basys, Nexys 2, or Nexys 3 board. Get up and running quickly from the basics to the 7-segment display, memory, VGA port, PS/2 port, and more - step-by-step, by example!
store.digilentinc.com/digital-design-using-digilent-fpga-...