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12 bit 4-stage pipeline RISC TIC-TAC-TOE playing CPU, 1994

For for our final project in our introduction to digital design course my lab partner and I decided that instead of designing the core of a CISC processor (microcode sucks!) that we would righteously design a 4 stage pipeline RISC processor, albeit only 12 bits - and make it play tic-tac-toe. We implemented branch predicition too!

 

It is an accumulator design, so only one register, the the 12-bits were divided into 4 bit opcodes, and 8 bits for data, all implicitly acting on the accumulator and started taking graduate level classes in graphics and image processing. Very cool stuff!

 

The opcodes were:

0000 - noop

0001 - not implemented

0010 - Jump

0011 - Store to Memory

0100 - And

0101 - Add

0110 - Subtract

0111 - Load from memory

1000 - Shift Right

1001 - Shift Left

1010 - Jump to Zero

1011 - Complement

1100 - Add immediate

1101 - And immediate

1110 - Subtract immediate

1111 - Load immediate

 

I wrote the assembler and two programs: a fibonacci sequence generator, and a tic-tac-toe program which was based on a decision tree of a pruned graph using the symmetry of the grid as shown in "the tinker toy computer" by genius Danny Hillis.

 

You can see the "board" in the lower middle which was implemented as memory mapped I/O.

 

I got bored of architecture after taking the graduate supercomputer architecture class which seemed like the end of hardware design had arrived. I switched to computer graphics just after Jurassic Park came out.

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Uploaded on June 28, 2006
Taken on June 28, 2006