DAC User Track: Thomas Harms of Infineon gives an overview on "Gap Analysis of Commercially Available Functional Verification Tools and Flows"

I had the good fortune to sit in on an intriguing summary of EDA gaps/ requirements in the functional verification tools and flows given by Thomas Harms of Infineon. Specifically, Thomas was speaking on behalf of the IEEE Design Technology Committee (DTC) – Study Group, which as you'll see from the paper's citation below comprises power users from a wide spectrum of companies. The good news was that most of the issues identified are already on our docket. The bad news is not all of them are (yet)!

 

Here is the full citation:

 

8U.6 — Invited: Gap Analysis of Commercially Available Functional Verification Tools and Flows

Speaker:Thomas Harms - Infineon Technologies, Neubiberg, Germany

Authors:Matthias Bauer - Infineon Technologies, Neubiberg, Germany

Thomas Dillinger - Oracle, Santa Clara, CA

Bjorn Fjellborg - Ericsson, Sweden

Bhadra Jay - Freescale Semiconductor, Inc., Austin, TX

Kim Joonyoung - Intel Corp., Santa Clara, CA

David Lacey - Hewlett-Packard Co., Fort Collins, CO

Jing Li - Broadcom Corp., San Jose, CA

Christopher J. Spandikow - IBM Corp., Austin, TX

Thomas Harms - Infineon Technologies, Neubiberg, Germany

 

Done